HD6412373R RENESAS [Renesas Technology Corp], HD6412373R Datasheet - Page 665

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HD6412373R

Manufacturer Part Number
HD6412373R
Description
Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
Examples of Cascaded Operation: Figure 11.18 illustrates the operation when counting upon
TCNT_2 overflow/underflow has been set for TCNT_1, TGRA_1 and TGRA_2 have been
designated as input capture registers, and the TIOC pin rising edge has been selected.
When a rising edge is input to the TIOCA1 and TIOCA2 pins simultaneously, the upper 16 bits of
the 32-bit data are transferred to TGRA_1, and the lower 16 bits to TGRA_2.
Figure 11.19 illustrates the operation when counting upon TCNT_2 overflow/underflow has been
set for TCNT_1, and phase counting mode has been designated for channel 2.
TCNT_1 is incremented by TCNT_2 overflow and decremented by TCNT_2 underflow.
TCNT_1
clock
TCNT_1
TCNT_2
clock
TCNT_2
TIOCA1,
TIOCA2
TGRA_1
TGRA_2
TCLKC
TCLKD
TCNT_2
TCNT_1
H'FFFF
H'03A1
Figure 11.18 Example of Cascaded Operation (1)
Figure 11.19 Example of Cascaded Operation (2)
FFFD
0000
FFFE
FFFF
0000
H'0000
0001
Rev.7.00 Mar. 18, 2009 page 597 of 1136
Section 11 16-Bit Timer Pulse Unit (TPU)
H'03A2
H'03A2
H'0000
0001
0002
0001
0000
H'0001
REJ09B0109-0700
FFFF
0000

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