HD6412373R RENESAS [Renesas Technology Corp], HD6412373R Datasheet - Page 871

• Manufacturer Part Number: HD6412373R
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

16.7
(1) Issue (retransmit) the start/stop conditions after the fall of the ninth clock is confirmed.
(2) Control WAIT in the I
(3) I
(4) Limitations on transfer rate setting values when using I
(5) Limitations on use of bit manipulation instructions to set MST and TRS when using I
Check SCLO in the I
When the start/stop conditions are issued (retransmitted) at the specific timing under the
following condition (i) or (ii), such conditions may not be output successfully. This does not
occur in other cases.
(i) When the rising of SCL falls behind the time specified in section 16.6, Bit Synchronous
(ii) When the bit synchronous circuit is activated by extending the low period of eighth and
When WAIT is set to 1, and SCL is driven low for two or more transfer clocks by the slave
device at the eighth and ninth clocks, the high period of ninth clock may be shortened. This
does not occur in other cases.
When operating in master receive mode with RDRF set to 1, SCL is driven low at the falling
edge of the eighth clock cycle. However, when ICDRR is read near the falling edge of the
eighth clock cycle, SCL is only fixed low for one clock cycle at the eighth clock cycle of the
next receive data, after which SCL is no longer fixed and the ninth clock cycle is output, even
if ICDRR is not read. This causes the receive data to overflow.
The following methods can be used to prevent this from occurring.
⎯ In master receive mode, complete processing to read ICDRR before the rising edge of the
⎯ In master receive mode, set RCVD to 1 and perform communication processing one byte at
master mode
When operating in multi-master mode and the IIC transfer rate setting of the MCU is slower
than that of another master device, an SCL of an unanticipated width may by output
occasionally. To prevent this, set the transfer rate to a value 1/1.8 or greater than the fastest
transfer rate among the other master devices. For example, if the fastest transfer rate setting
among the other master devices is 400 kbps, set the IIC transfer rate of the MCU to 223 kbps
(400/1.8) or higher.
interface 2 (IIC2) in multi-master mode
2
C bus interface 2 (IIC2) master receive mode
Circuit, by the load of the SCL bus (load capacitance or pull-up resistance)
ninth clocks, that is driven by the slave device
eighth clock cycle.
a time.
Usage Notes
2
C control register B (IICRB) to confirm the fall of the ninth clock.
2
C bus mode register (ICMR) to be set to 0.
Section 16 I
Rev.7.00 Mar. 18, 2009 page 803 of 1136
2
C bus interface 2 (IIC2) in multi-
2
C Bus Interface 2 (IIC2) (Option)
REJ09B0109-0700
2
C bus