HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 107

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Instruction
STC.L
STC.L
STC.L
STC.L
STC.L
STC.L
STC.L
STC.L
STC.L
STC.L
STS
STS
STS
STS.L
STS.L
STS.L
TRAPA #imm
Notes: *1 Minimum number of cycles before the chip enters the sleep state.
SSR,@–Rn
SPC,@–Rn
R0_BANK,@–Rn
R1_BANK,@–Rn
R2_BANK,@–Rn
R3_BANK,@–Rn
R4_BANK,@–Rn
R5_BANK,@–Rn
R6_BANK,@–Rn
R7_BANK,@–Rn
MACH,Rn
MACL,Rn
PR,Rn
MACH,@–Rn
MACL,@–Rn
PR,@–Rn
*2 For details, refer to section 4, Exception Handling.
1. The table shows the minimum number of cycles required for execution. In practice, the
2. For addressing modes with displacement (disp) as shown below, the assembler
a. If there is a conflict between an instruction fetch and a data access
b. If the destination register of a load instruction (memory → register) is also used by
number of execution cycles will be increased in the following conditions.
description in this manual indicates the value before it is scaled (x 1, x 2, or x 4)
according to the operand size to clarify the LSI operation. For details on assembler
description, refer to the description rules in each assembler.
the following instruction.
@ (disp:4, Rn) ; Register indirect with displacement
@ (disp:8, GBR) ; GBR indirect with displacement
@ (disp:8, PC) ; PC relative with displacement
disp:8, disp:12; PC relative
Instruction Code Operation
0100nnnn00110011
0100nnnn01000011
0100nnnn10000011
0100nnnn10010011
0100nnnn10100011
0100nnnn10110011
0100nnnn11000011
0100nnnn11010011
0100nnnn11100011
0100nnnn11110011
0000nnnn00001010
0000nnnn00011010
0000nnnn00101010
0100nnnn00000010
0100nnnn00010010
0100nnnn00100010
11000011iiiiiiii
Rn–4→Rn, SSR→(Rn)
Rn–4→Rn, SPC→(Rn)
Rn–4→Rn, R0_BANK→(Rn) √
Rn–4→Rn, R1_BANK→(Rn) √
Rn–4→Rn, R2_BANK→(Rn) √
Rn–4→Rn, R3_BANK→(Rn) √
Rn–4→Rn, R4_BANK→(Rn) √
Rn–4→Rn, R5_BANK→(Rn) √
Rn–4→Rn, R6_BANK→(Rn) √
Rn–4→Rn, R7_BANK→(Rn) √
MACH→Rn
MACL→Rn
PR→Rn
Rn–4→Rn, MACH→(Rn)
Rn–4→Rn, MACL→(Rn)
Rn–4→Rn, PR→(Rn)
Unconditional trap exception
occurs*
2
Rev. 1.00, 02/04, page 69 of 804
Privileged
Mode
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Cycles T Bit
1
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1
1
1
1
1
1
1
1
1
1
1
1
1
1
8
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