HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 703

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Bit
31 to 16 
15
14
13
12
11
10
Bit Name
SCMFCA
SCMFCB
SCMFDA
SCMFDB
PCTE
PCBA
Initial
Value R/W
All 0
0
0
0
0
0
0
R
R/W
R/W
R/W
R/W
R/W
R/W
L Bus Cycle Condition Match Flag A
L Bus Cycle Condition Match Flag B
Description
Reserved
These bits are always read as 0. The write value should
always be 0. If 1 is written to these bits, correct operation
cannot be guaranteed.
When the L bus cycle condition in the break conditions set
for channel A is satisfied, this flag is set to 1 (not cleared to
0). In order to clear this flag, write 0 into this bit.
0: The L bus cycle condition for channel A does not match
1: The L bus cycle condition for channel A matches
When the L bus cycle condition in the break conditions set
for channel B is satisfied, this flag is set to 1 (not cleared to
0). In order to clear this flag, write 0 into this bit.
0: The L bus cycle condition for channel B does not match
1: The L bus cycle condition for channel B matches
I Bus Cycle Condition Match Flag A
When the I bus cycle condition in the break conditions set
for channel A is satisfied, this flag is set to 1 (not cleared to
0). In order to clear this flag, write 0 into this bit.
0: The I bus cycle condition for channel A does not match
1: The I bus cycle condition for channel A matches
I Bus Cycle Condition Match Flag B
When the I bus cycle condition in the break conditions set
for channel B is satisfied, this flag is set to 1 (not cleared to
0). In order to clear this flag, write 0 into this bit.
0: The I bus cycle condition for channel B does not match
1: The I bus cycle condition for channel B matches
PC Trace Enable
0: Disables PC trace
1: Enables PC trace
PC Break Select A
Selects the break timing of the instruction fetch cycle for
channel A as before or after instruction execution.
0: PC break of channel A is set before instruction execution
1: PC break of channel A is set after instruction execution
Rev. 1.00, 02/04, page 665 of 804