HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 594

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Rev. 1.00, 02/04, page 556 of 804
Bit
10
9, 8
7
6
Bit Name
EP3i TS

EP2o FULL
EP2i EMPTY 1
Initial
Value
0
All 0
0
R/W
R/W
R
R*
R*
1
1
Description
EP3i (Iso in) Normal Transmission
Flag indicating the FIFO state of EP3i.
After the SOF packet is received, the FIFO buffer is
switched automatically. The FIFO buffer which has
transmitted the data to the host in the previous frame
(before SOF reception) can be written to from the CPU.
This bit shows the transmitting state in front of this one.
[Setting condition]
When a transmission was carried out normally in the
previous frame.
[Clearing conditions]
•
•
Reserved
These bits are always read as 0. The write value should
always be 0. If 1 is written to these bits, correct operation
cannot be guaranteed.
EP2o (Bulk out) FIFO Full
[Setting condition]
The FIFO buffer of EP2o has a dual-buffer configuration,
and this bit is set when at least one of the FIFO buffer is
full.
[Clearing conditions]
•
•
Note: EP2o FULL is a status bit, and cannot be
EP2i (Bulk in) FIFO Empty
[Setting condition]
•
•
[Clearing condition]
When both FIFO buffers are not empty.
Note: EP2i EMPTY is a status bit, and cannot be
At a reset
When 0 is written to by CPU
At a reset
When both FIFO buffers are empty.
At a reset
The FIFO buffer of EP2i has a dual-buffer
configuration, and this bit is set when at least one of
the FIFO buffer is empty.
cleared.
cleared.