HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 259

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

9.3
9.3.1
In the architecture of this LSI, the logical spaces have 32-bit address spaces. The cache access
method is shown by the upper three bits. For details see section 5, Cache. The remaining 29 bits
are mapped in 512-Mbyte physical address space that are used for division of the space into eight
areas. The BSC performs control for this 29-bit physical space. Figure 9.2 shows the mapping
from the logical address space to the physical address space. Area 1 is used for the internal I/O,
and area 2 and area 5 to area 7 are reserved. The other three areas (area 0, area 3, and area 4) are
used as external address spaces.
As listed in table 9.2, this LSI can connect each type of memories to three area of an external
address space among the physical address spaces divided into eight areas, respectively. And it
outputs chip select signals (CS0, CS3, and CS4) for each of them. CS0 is asserted during area 0
access; CS4 is asserted during area 4 access.
H'C0000000
H'A0000000
H'E0000000
H'00000000
H'20000000
H'40000000
H'60000000
H'80000000
Area Overview
Area Division
Figure 9.2 Logical Address Space and Physical Address Space
Logical address space
P0
P1
P2
P3
P4
Physical address space
Area 2 (Reserved area)
Area 5 (Reserved area)
Area 6 (Reserved area)
Area 7 (Reserved area)
Rev. 1.00, 02/04, page 221 of 804
Area 1 (Internal I/O)
Area 0 (CS0)
Area 3 (CS3)
Area 4 (CS4)
H'00000000
H'04000000
H'08000000
H'0C000000
H'10000000
H'14000000
H'1FFFFFFF