HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 12

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 8 Interrupt Controller (INTC)............................................................... 199
8.1
8.2
8.3
8.4
8.5
Section 9 Bus State Controller (BSC) ............................................................... 217
9.1
9.2
9.3
9.4
Rev. 1.00, 02/04, page xii of xxxviii
7.3.1
7.3.2
7.3.3
7.3.4
Features............................................................................................................................. 199
Input/Output Pins.............................................................................................................. 201
Register Descriptions........................................................................................................ 201
8.3.1
8.3.2
8.3.3
8.3.4
8.3.5
8.3.6
8.3.7
Interrupt Sources............................................................................................................... 211
8.4.1
8.4.2
8.4.3
8.4.4
Operation .......................................................................................................................... 214
8.5.1
8.5.2
Overview........................................................................................................................... 217
9.1.1
Input/Output Pins.............................................................................................................. 220
Area Overview.................................................................................................................. 221
9.3.1
9.3.2
9.3.3
9.3.4
Register Descriptions........................................................................................................ 224
9.4.1
9.4.2
9.4.3
9.4.4
9.4.5
9.4.6
Interrupt Mask Registers 0, 1, 4 to 6, and 9
(IMR0, IMR1, IMR4 to IMR6, and IMR9) ......................................................... 208
Interrupt Mask Clear Registers 0, 1, 4 to 6, and 9
(IMCR0, IMCR1, IMCR4 to IMCR6, and IMCR9) ............................................ 210
Page Conflict ....................................................................................................... 197
Bus Conflict ......................................................................................................... 197
Cache Settings ..................................................................................................... 197
sleep mode ........................................................................................................... 198
Interrupt Priority Registers A to H (IPRA to IPRH)............................................ 202
Interrupt Control Register 0 (ICR0)..................................................................... 204
Interrupt Control Register 1 (ICR1)..................................................................... 205
Interrupt Control Register 2 (ICR2)..................................................................... 207
Interrupt Request Register 0 (IRR0) .................................................................... 208
NMI Interrupt....................................................................................................... 211
IRQ Interrupts...................................................................................................... 211
On-Chip Peripheral Module Interrupts ................................................................ 212
Interrupt Exception Handling and Priority........................................................... 212
Interrupt Sequence ............................................................................................... 214
Multiple Interrupts ............................................................................................... 216
Features................................................................................................................ 217
Area Division....................................................................................................... 221
Shadow Area........................................................................................................ 222
Address Map........................................................................................................ 223
Data Bus Width.................................................................................................... 224
Common Control Register (CMNCR) ................................................................. 225
CSn Space Bus Control Register (CSnBCR) (n=0, 3, 4) ..................................... 227
CSn Space Wait Control Register (CSnWCR) (n=0, 3, 4) .................................. 231
SDRAM Control Register (SDCR)...................................................................... 242
Refresh Timer Control/Status Register (RTCSR)................................................ 245
Refresh Timer Counter (RTCNT)........................................................................ 246