HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 444

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

15.3.13 Control Data Assign Register (SICDAR)
SICDAR is a 16-bit readable/writable register that specifies the position of the control data in a
frame (slot number). SICDAR can be specified only when the FL bit in SIMDR is specified as
1xxx (x: Don't care).
Rev. 1.00, 02/04, page 406 of 804
Bit
11
10
9
8
7
6 to 4
3
2
1
0
Bit
15
14 to 12
Bit Name
RDLA3
RDLA2
RDLA1
RDLA0
RDRE
—
RDRA3
RDRA2
RDRA1
RDRA0
Bit Name
CD0E
—
Initial
Value
0
0
0
0
0
All 0
0
0
0
0
Initial
Value
0
All 0
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R
Description
Receive Left-Channel Data Assign
Specify the position of left-channel data in a receive
frame as B'0000 (0) to B'1110 (14).
1111: Setting prohibited
•
Receive Right-Channel Data Enable
0: Disables right-channel data reception
1: Enables right-channel data reception
Reserved
These bits are always read as 0. The write value should
always be 0. If 1 is written to these bits, the operation is
not guaranteed.
Receive Right-Channel Data Assign
Specify the position of right-channel data in a receive
frame as B'0000 (0) to B'1110 (14).
1111: Setting prohibited
•
Description
Control Channel 0 Data Enable
0: Disables transmission and reception of control
1: Enables transmission and reception of control
Reserved
These bits are always read as 0. The write value should
always be 0. If 1 is written to these bits, the operation is
not guaranteed.
Receive data for the left channel is stored in the
SIRDL bit in SIRDR.
Receive data for the right channel is stored in the
SIRDR bit in SIRDR.
channel 0 data
channel 0 data