HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 127

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Here, a branch includes a return from an exception handling routine. If an exception whose return
address is placed in an instruction following the repeat detection instruction occurs, the repeat
control cannot be returned correctly. Accordingly, an exception acceptance is restricted from the
repeat detection instruction to the repeat end instruction. Exceptions such as interrupts that can be
retained by the CPU are retained. For exceptions that cannot be retained by the CPU, a transition
to an exception occurs but a program cannot be returned to the previous execution state correctly.
For details, refer to section 4, Exception Handling.
Notes: 1. If a TRAPA instruction is used as a repeat detection instruction, an instruction
5. Branch from a repeat detection instruction
6. Program counter during repeat control
 If a subroutine call is used in the repeat loop, a delayed slot instruction of the subroutine
If a repeat detection instruction is a delayed slot instruction of a delayed branch instruction or a
branch instruction, a repeat loop can be acknowledged when a branch does not occur in a
branch instruction. If a branch occurs in a branch instruction, a repeat control is not
performed and a branch destination instruction is executed.
If RC[11:0] ≥ 2, the program counter (PC) value is not correct for instructions two instructions
following a repeat detection instruction. In a repeat loop consisting of one to three
instructions, the PC indicates the correct value (instruction address + 4) for an instruction
(repeat start instruction) following a repeat detect ion instruction but the PC continues to
indicate the same address (repeat start instruction address) from the subsequent instruction to a
repeat end instruction. In a repeat loop consisting of four or more instructions, the PC
indicates the correct value (instruction address + 4) for an instruction following a repeat detect
ion instruction, but PC indicates the RS and (RS +2) for instructions two and three instructions
following the repeat detection instruction. The correct operation cannot be guaranteed for the
incorrect PC values.
Accordingly, PC relative addressing instructions placed two or more instructions following the
repeat detection instruction cannot be executed correctly and the correct results cannot be
obtained.
call instruction must be placed before a repeat detection instruction.
2. If a SLEEP instruction is placed following a repeat detection instruction, a transition to
following the repeat detection instruction is regarded as a return address. In this case, a
control cannot be returned to the repeat control correctly. In a TRAPA instruction, an
address of an instruction following the repeat detection address is regarded as return
address. Accordingly, to return to the repeat control correctly, place a return address
prior to the repeat detection instruction.
the power-down state or an exception acceptance such as interrupts can be performed
correctly. In this case, however, the repeat control cannot be returned correctly. To
return to the repeat control correctly, the SLEEP instruction must be placed prior to the
repeat detection instruction.
Rev. 1.00, 02/04, page 89 of 804