HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 215

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

5.1
• Capacity: 16 kbytes
• Structure: Instructions/data mixed, 4-way set associative
• Locking: Way 2 and way 3 are lockable
• Line size: 16 bytes
• Number of entries: 256 entries/way
• Write system: Write-back/write-through is selectable for spaces P0, P1, P3, and U0
• Replacement method: Least-recently used (LRU) algorithm
5.1.1
The cache mixes instructions and data and uses a 4-way set associative system. It is composed of
four ways (banks), and each of which is divided into an address section and a data section. Each of
the address and data sections is divided into 256 entries. The entry data is called a line. Each line
consists of 16 bytes (4 bytes × 4). The data capacity per way is 4 kbytes (16 bytes × 256 entries) in
the cache as a whole (4 ways). The cache capacity is 16 kbytes as a whole. Figure 5.1 shows the
cache structure.
CASH001B_00020030200
individually.
Group 1 (P0, P3, and U0 areas)
Group 2 (P1 area)
Features
Cache Structure
Entry 255
Entry 0
Entry 1
.
.
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.
24 (1 + 1 + 22) bits
V U Tag address
Address array (ways 0 to 3)
Figure 5.1 Cache Structure
Section 5 Cache
255
0
1
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.
LW0
LW0 to LW3: Longword data 0 to 3
128 (32 × 4) bits
LW1
LW2
Data array (ways 0 to 3)
Rev. 1.00, 02/04, page 177 of 804
LW3
255
0
1
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LRU
6 bits