HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 559

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

19.3.5
Each enable bit in HIER controls whether to generate an interrupt by an event related to the
HcInterruptStatus register. A hardware interrupt is requested to the CPU when an event bit in the
HcInterruptStatus register is set, a corresponding bit in the HcInterruptEnable register is set, and
the MasterInterruptEnable (MIE) bit is set. As a result, the exception code (H'A00) of the host
controller interrupt (USBHI) is set in the interrupt event register 2 (INTEVT2) and the exception
handling is started (the USBHI exception code is used in common regardless of the content of the
interrupt generation event). Therefore, the USBHI exception code can be used when an interrupt
generation is detected by the host controller driver. For details on the interrupt event register 2
(INTEVT2), see section 4, Exception Handling, and for details on the exception code and interrupt
processing of the host controller interrupt (USBHI), see section 8, Interrupt Controller (INTC).
Writing 1 in this register sets the corresponding bit, while writing 0 does not change it. When the
specified bit needs to be set, writing data in which only the corresponding bit is 1 enables the bit to
be set independently without checking the states of other bits.
HIER is in conjunction with the HcInterruptDisable register which is described later. Therefore
when a specific bit needs to be cleared to 0, writing 1 to the corresponding bit in the
HcInterruptDisable register automatically clears the corresponding bit in this register.
Bit
31
30
Bit Name
MIE
OC
HcInterruptEnable Register (HIER)
Initial
Value
0
0
R/W
R/W
R/W
Description
Master Interrupt Enable
When this bit is set to 1, an interrupt generation by the
event specified in another bit in this register is enabled.
This is used by the host controller driver so that the
master interrupt is enabled. When 1 is written to the MIE
bit in the HcInterruptDisable register, this bit is cleared to
0.
0: This bit is ignored.
1: Enables interrupt generation due to the event specified
Ownership Change Interrupt Enable
When this bit is set to 1, an interrupt generation by the
Ownership Change event is enabled. When 1 is written to
the OC bit in the HcInterruptDisable register, this bit is
cleared to 0.
0: This bit is ignored.
1: Enables interrupt generation due to the Ownership
by other bit.
Change event.
Rev. 1.00, 02/04, page 521 of 804