HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 361

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

CKIO
Transfer source
Transfer destination
A23 to A0
address
address
CSn
D15 to D0
RD
WEn
DACKn
(Active-Low)
Data read cycle
Data write cycle
(1st cycle)
(2nd cycle)
Note: In transfer between external memories, with DACK output in the read cycle,
DACK output timing is the same as that of CSn.
Figure 10.6 Example of DMA Transfer Timing in Dual Mode (Source: Ordinary memory,
Destination: Ordinary memory)
2. Single Address Mode
In single address mode, either the transfer source or transfer destination peripheral device is
accessed (selected) by means of the DACK signal, and the other device is accessed by address.
In this mode, the DMAC performs one DMA transfer in one bus cycle, accessing one of the
external devices by outputting the DACK transfer request acknowledge signal to it, and at the
same time outputting an address to the other device involved in the transfer. For example, in
the case of transfer between external memory and an external device with DACK shown in
figure 10.7, when the external device outputs data to the data bus, that data is written to the
external memory in the same bus cycle.
Rev. 1.00, 02/04, page 323 of 804