HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 513

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

16.4.4
The clock synchronous mode is described below.
64-stage FIFO buffers are provided for both transmission and reception, reducing the CPU
overhead and enabling fast, continuous communication to be performed.
The operating clock source is selected using the serial mode register (SCSMR). The SCIF clock
source is determined by the CKE1 and CKE0 bits in the serial control register (SCSCR).
• Transmit/receive format: Fixed 8-bit data
• Indication of the number of data bytes stored in the transmit and receive FIFO registers
• Internal clock or external clock used as the SCIF clock source
When using a modem function and the receive FIFO (SCFRDR) is at least the number of the
RTS output trigger, the RTS signal goes high.
Figure 16.11 shows an example of operation for the RTS control.
When the internal clock is selected:
The SCIF operates on the baud rate generator clock and outputs a serial clock from SCK pin.
When the external clock is selected:
The SCIF operates on the external clock input through the SCK pin.
Transmit data
TxD
RTS
Clock Synchronous Mode
Start
bit
0
D0
RTS goes high when receive data is
at least number of RTS output trigger
Figure 16.11 RTS Control Operation
D1
D6
D7
Parity
bit
0/1
Stop
bit
RTS goes low when receive data is
less than number of RTS output trigger
Rev. 1.00, 02/04, page 475 of 804