HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 360

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Figure 10.6 shows an example of DMA transfer timing in dual address mode.
Rev. 1.00, 02/04, page 322 of 804
Auto request, external request, and on-chip peripheral module request are available for the
transfer request. DACK can be output in read cycle or write cycle in dual address mode. The
AM bit of the channel control register (CHCR) can specify whether the DACK is output in
read cycle or write cycle.
The SAR value is an address, data is read from the transfer source module,
and the data is temporarily stored in the DMAC.
The DAR value is an address and the value stored in the data buffer in the
DMAC is written to the transfer destination module.
Data buffer
Data buffer
Figure 10.5 Data Flow of Dual Address Mode
DMAC
DMAC
SAR
DAR
SAR
DAR
Second bus cycle
First bus cycle
Transfer destination
Transfer destination
Transfer source
Transfer source
Memory
Memory
module
module
module
module