HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 321

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Power-On Sequence: In order to use the SDRAM, mode setting must first be performed after
powering on. To perform SDRAM initialization correctly, the bus state controller registers must
first be set, followed by a write to the SDRAM mode register by accessing the SDMR3 register. In
SDRAM mode register setting, the address signal value at that time is latched by a combination of
the CS3, RAS, CAS, and RD/WR signals. If the value to be set is X, the bus state controller
provides for value X to be written to the SDRAM mode register by performing a write to address
H'A4FD5000 + X for SDRAM. In this operation the data is ignored. To set burst read/single write
(burst length 1) or burst read/burst write (burst length 1), CAS latency 2 to 3, wrap type =
sequential, and burst length 1 supported by the LSI, arbitrary data is written in a word-size access
to the addresses shown in table 9.11. In this time 0 is output at the external address pins of A12 or
later.
Table 9.11 Access Address in SDRAM Mode Register Write
• Setting for Area 3 (SDMR3)
Mode register setting timing is shown in figure 9.27. A PALL command (all bank pre-charge
command) is firstly issued. A REF command (auto refresh command) is then issued eight times.
An MRS command (mode register write command) is finally issued. Idle cycles, of which number
is specified by the TRP[1:0] bits in CS3WCR, are inserted between the PALL and the first REF.
Idle cycles, of which number is specified by the TRC[1:0]bits in CS3WCR, are inserted between
REF and REF, and between the 8th REF and MRS. Idle cycles, of which number is one or more,
are inserted between the MRS and a command to be issued next.
It is necessary to keep idle time of certain cycles for SDRAM before issuing PALL command after
power-on. Refer the manual of the SDRAM to be used for the idle time to be needed. When the
pulse width of the reset signal is longer then the idle time, mode register setting can be started
immediately after the reset, but care should be taken when the pulse width of the reset signal is
shorter than the idle time.
Data Bus Width
16 bits
Data Bus Width
16 bits
Burst read/single write (burst length 1):
Burst read/burst write (burst length 1):
CAS Latency
2
3
CAS Latency
2
3
Access Address
H'A4FD5040
H'A4FD5060
Access Address
H'A4FD5440
H'A4FD5460
Rev. 1.00, 02/04, page 283 of 804
External Address Pin
H'0000440
H'0000460
External Address Pin
H'0000040
H'0000060