HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 230

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

6.2
6.2.1
The 8/16/32-bit access by the CPU can be performed via the L bus or I bus. Methods for accessing
by the CPU are via the L bus from the virtual addresses, and via the I bus from the physical
addresses. As long as a conflict on the page does not occur, access via the L bus is performed in
one cycle. Several cycles are necessary for accessing via the I bus. According to the CPU
operating mode, access from the CPU is as follows:
Privileged mode and privileged DSP mode (SR. MD = 1): The X/Y memory can be accessed by
the CPU from spaces P0 and P2.
User DSP mode (SR.MD = 0 and SR.DSP = 1): The X/Y memory can be accessed by the CPU
from spaces U0 and Uxy.
User mode (SR.MD = 0 and SR.DSP = 0): The X/Y memory can be accessed by the CPU from
space U0.
6.2.2
The16/32-bit access by the DSP can be performed via the L bus or I bus. A 16-bit access by the
DSP can be performed via the X and Y buses. Methods for accessing from the DSP differ
according to instructions.
With a X data transfer instruction and a Y data transfer instruction, the X/Y memory is always
accessed via the X bus or Y bus. As long as a conflict on the page does not occur, access via the X
bus or Y bus is performed in one cycle. The X memory access via the X bus and the Y memory
access via the Y bus can be performed simultaneously.
In the case of a single data transfer instruction, methods for accessing from the DSP are directly
via the L bus from the virtual addresses, and via the I bus from the physical addresses. As long as
a conflict on the page does not occur, access via the L bus is performed in one cycle. Several
cycles are necessary for accessing via the I bus. According to the CPU operating mode, access
from the CPU is as follows:
Privileged DSP mode (SR. MD = 1 and SR.DSP = 1): The X/Y memory can be accessed by the
DSP from spaces P0 and P2.
User DSP mode (SR.MD = 0 and SR.DSP = 1): The X/Y memory can be accessed by the DSP
from spaces U0 and Uxy.
Rev. 1.00, 02/04, page 192 of 804
Access from DSP
Operation
Access from CPU