HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 485

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Bit
6
5
4
3, 2
Bit Name
RIE
TE
RE

0
0
0
All 0
Initial
Value
R/W
R/W
R/W
R/W
R
Description
Receive Interrupt Enable
Enables or disables generation of a receive-FIFO-data-full
interrupt request when the RDF flag in SCSSR is set to 1.
0: Receive-FIFO-data-full interrupt request disabled*
1: Receive-FIFO-data-full interrupt request enabled
Note: * The interrupt requests is cleared by reading 1 from the
Transmit Enable
Enables or disables the start of serial transmission by the
SCIF.
0: Transmission disabled
1: Transmission enabled*
Note: * The serial mode register (SCSMR) and FIFO control
Receive Enable
Enables or disables the start of serial reception by the SCIF.
0: Reception disabled*
1: Reception enabled*
Notes: 1. Clearing the RE bit to 0 does not affect the DR,
Reserved
These bits are always read as 0. The write value should
always be 0. If 1 is written to these bits, correct operation
cannot be guaranteed.
RDF flag, then clearing the flag to 0, or clearing the
RIE bit to 0.
register (SCFCR) settings must be made, the transmit
format decided, and the transmit FIFO reset, before
the TE bit is set to 1. If settings of above registers are
changed with the TE bit enabled, the operation cannot
be guaranteed.
2. The serial mode register (SCSMR) and FIFO
ER, BRK, RDF, FER, PER, and ORER flags,
which retain their state.
control register (SCFCR) settings must be made,
the receive format decided, and the receive FIFO
reset, before the RE bit is set to 1. If settings of
above registers are changed with the RE bit
enabled, the operation cannot be guaranteed.
2
1
Rev. 1.00, 02/04, page 447 of 804