HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 815

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HD6417660

Manufacturer Part Number
HD6417660
Description
Renesas 32-Bit RISC Microcomputer
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
28.3.8
Table 28.9 SIOF Module Signal Timing
Conditions:
Notes: 1. t
Item
SIOF_MCLK clock input cycle time
SIOF_MCLK input high level width
SIOF_MCLK input low level width
SIOF_SCK clock cycle time
SIOF_SCK output high level width
SIOF_SCK output low level width
SIOF_SYNC output delay time
SIOF_SCK input high level width
SIOF_SCK input low level width
SIOF_SYNC input setup time
SIOF_SYNC input hold time
SIOF_TXD output delay time
SIOF_RXD input setup time
SIOF_RXD input hold time
Slave select setup time
Slave select hold time
2. t
SIOF Module Signal Timing
PCYC
SICYC
/2 × n is defined according to the SSAST1 and SSAST0 bits in SPICR.
V
Ta = –40 to 85°C
is a cycle time of a peripheral clock (Pφ).
CC
= 2.7 to 3.6 V, V
SIOF_MCLK
Figure 28.49 SIOF_MCLK Input Timing
CC
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
MCYC
MWH
MWL
SICYC
SWHO
SWLO
FSD
SWHI
SWLI
FSS
FSH
STDD
SRDS
SRDH
SSS
SSH
_28= 2.7 to 3.0 V, AV
t
MWH
Min
t
0.4 × t
0.4 × t
t
0.4 × t
0.4 × t
0.4 × t
0.4 × t
20
20
20
10
t
t
PCYC
pcyc
SICYC
SICYC
t
MCYC
/2 × n*
/2 × n*
MCYC
MCYC
SICYC
SICYC
SICYC
SICYC
t
MWL
2
2
−20 
CC
= 2.7 to 3.6 V, V
Rev. 1.00, 02/04, page 777 of 804
Max
20
20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DD
Figure
28.49
28.49
28.49
28.50 to 28.54
28.50 to 28.53
28.50 to 28.53
28.50 to 28.53
28.54
28.54
28.54
28.54
28.50 to 28.54
28.50 to 28.54
28.50 to 28.54
28.55 to 28.56
28.55 to 28.56
= 1.4 to 1.6 V,

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