HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 705

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

25.2.10 Execution Times Break Register (BETR)
BETR is a 16-bit readable/writable register. When the execution-times break condition of channel
B is enabled, this register specifies the number of execution times to make the break. The
maximum number is 2
break is issued when the break condition is satisfied after BETR becomes H'0001.
Note: If the break condition of channel B is a break condition of instruction fetch cycle and the
Instruction
RTE
DMULS.L Rm, Rn
DMULU.L Rm, Rn
MAC.L @Rm+,@Rn+
MAC.W @Rm+,@Rn+
MUL.L Rm, Rn
AND.B #imm,@(R0, GBR)
OR.B #imm,@(R0, GBR)
TAS.B @Rn
TST.B #imm,@(R0, GBR)
XOR.B #imm,@(R0, GBR)
LDC Rm,SR
LDC Rm,GBR
Bit
15 to 12 
11 to 0
break instructions correspond to the following instructions, the BETR is not decremented by
1 every time when a break is occurred. Refer to the following for the decremented value.
Bit Name
BET11 to
BET0
12
Initial
Value R/W Description
All 0
All 0
– 1 times. When a break condition is satisfied, it decreases BETR. A
Countdown Value
R
R/W Number of Execution Times
4
2
2
2
2
3
3
3
3
3
3
4
4
Reserved
These bits are always read as 0. The write value should
always be 0. If 1 is written to these bits, correct operation
cannot be guaranteed.
Rev. 1.00, 02/04, page 667 of 804