HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 97

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Notes: 1. The table shows the minimum number of execution states. In practice, the number of
Instruction
Indicated by mnemonic.
Legend
OP.Sz SRC, DEST
Rm: Source register
Rn:
imm: Immediate data
disp: Displacement
OP:
Sz:
SRC: Source
DEST: Destination
Destination register
Operation code
Size
2. Scaled (x 1, x 2, or x 4) according to the instruction operand size, etc.
a.
b.
instruction execution states will be increased in cases such as the following:
When there is a conflict between an instruction fetch and a data access
When the destination register of a load instruction (memory → register) is also
used by the following instruction
Instruction Code
Indicated in MSB ↔
LSB order.
Legend
mmmm: Source register
nnnn: Destination register
iiii:
dddd:
0000: R0
0001: R1
.........
1111: R15
Immediate data
Displacement *
2
Operation
Indicates summary of
operation.
Legend
→, ←: Transfer direction
(xx):
M/Q/T: Flag bits in SR
&:
|:
^:
~:
<<n: n-bit left shift
>>n: n-bit right shift
Logical AND of each bit
Logical OR of each bit
Exclusive logical OR of
each bit
Logical NOT of each bit
Memory operand
Rev. 1.00, 02/04, page 59 of 804
Privilege
Indicates a
privileged
instruction.
Execution
States
Value
when no
wait states
are
inserted *
1
T Bit
Value of T
bit after
instruction
is executed
Legend
—: No
change