HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 168

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

+32. Here, a negative value means the right shift, and a positive value means the left shift. It is
possible for any source 2 operand to specify from –64 to +63 but the result is unknown if an
invalid shift value is specified. In case of a shift with an immediate operand instruction, the source
1 operand must be the same register as the destination’s. This operation is executed in the DSP
stage, as shown in figure 3.10 as well as in ALU fixed-point arithmetic operations. The DSP stage
is the same stage as the MA stage in which memory access is performed.
Every time an arithmetic shift operation is executed, the DC, N, Z, V, and GT bits in DSR are
basically updated in accordance with the operation result. In case of a conditional operation, they
are not updated even though the specified condition is true and the operation is executed. In case
of an unconditional operation, they are always updated in accordance with the operation result.
The definition of the DC bit is selected by the CS[2:0] (DC bit condition selection) bits in DSR.
The DC bit result is:
1. Carry or Borrow Mode: CS[2:0] = B'000
2. Negative Value Mode: CS[2:0] = B'001
3. Zero Value Mode: CS[2:0] = B'010
4. Overflow Mode: CS[2:0] = B'011
5. Signed Greater Than Mode: CS[2:0] = B'100
6. Signed Greater Than or Equal Mode: CS[2:0] = B'101
The N bit always indicates the same state as the DC bit set in negative value mode by the CS[2:0]
bits. See the negative value mode part above. The Z bit always indicates the same state as the DC
bit set in zero value mode by the CS[2:0] bits. See the zero value mode part above. The V bit
always indicates the same state as the DC bit set in overflow mode by the CS[2:0] bits. See the
overflow mode part above. The GT bit always indicates the same state as the DC bit set in signed
greater than mode by the CS[2:0] bits. See the signed greater than mode part above.
• Overflow Protection
Logical Shift: Figure 3.18 shows the logical shift operation flow.
Rev. 1.00, 02/04, page 130 of 804
The DC bit indicates the last shifted out data as the operation result.
The DC bit is set to 1 when the operation result is a negative value, and cleared to 0 when the
operation result is zero or a positive value.
The DC bit is set to 1 when the operation result is zero; otherwise it is cleared to 0.
The DC bit is set to 1 when an overflow occurs.
The DC bit is always cleared to 0.
The DC bit is always cleared to 0.
The S bit in SR is also effective for arithmetic shift operation in the DSP unit. See section
3.5.11, Overflow Protection, for details.