HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 584

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

19.4
19.4.1
The data storage format (endian) of the USB host controller is in conjunction with the CPU endian
specification by the MD5 pin. Therefore, when the CPU is operated as big endian, transfer data of
the USB host controller must be treated in big-endian order. When the CPU is operated as little
endian, transfer data of the USB host controller must be treated in little-endian order.
19.4.2
ED (endpoint descriptor) and TD (transfer descriptor) that define each transfer transaction of the
USB host controller must be aligned so that each Dword corresponds to the longword boundary
(addresses 4n to 4n + 3) of the memory. In this case, the difference of endian has no influence.
19.5
19.5.1
Following procedure should be used when the software reset is issued ( the HCR bit of the HCSR
register is set to 1) while USB state is Operational, or when the USB state is shifted from the
Operational state to the Reset state ( the HCFS1/0 bit of the HCTLR register is cleared to 00).
1. Each list processing is discontinued. (The BLE bit, the CLE bit, the IE bit, and the PLE bit of
2. Wait until the SOF interrupt from the USB host controller is detected twice. (SF bit interrupt of
3. Put the USB into the Suspend state by setting the HCFS1/0 bits of the HCTLR register to 11.
4. The reset processing is executed.
Rev. 1.00, 02/04, page 546 of 804
the HCTLR register are cleared to 0. )
HISR register)
Data Storage Format of USB Host Controller
Storage Format of Transferred Data
Storage Format of Descriptor
Usage Restrictions of USB Host Controller
Restriction of Reset Control