HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 717

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

(Example 1-6)
• Register specifications
Break Condition Specified for L Bus Data Access Cycle:
(Example 2-1)
• Register specifications
BARA = H'00008404, BAMRA = H'00000FFF, BBRA = H'0054, BARB = H'00008010,
BAMRB = H'00000006, BBRB = H'0054, BDRB = H'00000000, BDMRB = H'00000000,
BRCR = H'00000400
Specified conditions: Channel A/channel B independent mode
 Channel A
 Channel B
BARA = H'00123456, BAMRA = H'00000000, BBRA = H'0064, BARB = H'000ABCDE,
BAMRB = H'000000FF, BBRB = H'006A, BDRB = H'0000A512, BDMRB = H'00000000,
BRCR = H'00000080
Specified conditions: Channel A/channel B independent mode
 Channel A
 Channel B
Address:
Bus cycle:
Address: H'00008010, Address mask: H'00000006
Data:
Bus cycle:
A user break occurs after an instruction with addresses H'00008000 to H'00008FFE is
executed or before an instruction with addresses H'00008010 to H'00008016 are executed.
Address: H'00123456, Address mask: H'00000000
Bus cycle: L bus/data access/read (operand size is not included in the condition)
Address: H'000ABCDE, Address mask: H'000000FF
Data:
Bus cycle: L bus/data access/write/word
On channel A, a user break occurs with longword read from address H'00123454, word
read from address H'00123456, or byte read from address H'00123456. On channel B, a
user break occurs when word H'A512 is written in addresses H'000ABC00 to
H'000ABCFE.
H'00000000, Data mask: H'00000000
H'0000A512, Data mask: H'00000000
H'00008404, Address mask: H'00000FFF
L bus/instruction fetch (after instruction execution)/read (operand size is not
included in the condition)
L bus/instruction fetch (before instruction execution)/read (operand size is
not included in the condition)
Rev. 1.00, 02/04, page 679 of 804