HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 626

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HD6417660

Manufacturer Part Number
HD6417660
Description
Renesas 32-Bit RISC Microcomputer
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
Setup Stage:
Rev. 1.00, 02/04, page 588 of 804
Notes: *1 In the setup stage, the application analyzes command data from the host requiring processing by
Receive 8-byte command
SETUP token reception
reception complete flag
*2 When the transfer direction is control-out, the EP0i transfer request interrupt required in the status
(IFR0/SETUP TS = 1)
Set setup command
to be processed by
the application, and determines the subsequent processing (for example, data stage direction, etc.).
stage should be enabled here. When the transfer direction is control-in, this interrupt is not required
and should be disabled.
To data stage
data in EP0s
application?
Command
USB function
Yes
Figure 20.7 Setup Stage Operation
No
processing by
Interrupt request
this module
Automatic
Clear EP0o FIFO (FCLR/EP0oCLR = 1)
Clear EP0i FIFO (FCLR/EP0iCLR = 1)
To control-in
Write 1 to EP0s read complete bit
data stage
Determine data stage direction
Read 8-byte data from EP0s
Decode command data
(TRG/EP0s RDFN = 1)
(IFR0/SETUP TS = 0)
Clear SETUP TS flag
Application
*2
To control-out
data stage
*1

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