PEF2256 INFINEON [Infineon Technologies AG], PEF2256 Datasheet - Page 135

• Manufacturer Part Number: PEF2256
• Description: E1/T1/J1 Framer and Line Interface Component for Long- and Short-Haul Applications
• Manufacturer: INFINEON [Infineon Technologies AG]

Table 31
Channel
Translation
Mode 0
FS/DL
1
2
3
–
4
5
6
–
7
8
9
–
10
11
12
– : FF
In one frame or short buffer mode the delay through the receive buffer is reduced to an
average delay of 96 or 48 bits. In bypass mode the time slot assigner is disabled. In this
case SYPR programmed as input is ignored. Slips are performed in all buffer modes
except bypass mode. After a slip is detected the read pointer is adjusted to one half of
the current buffer size.
Table 32
User’s Manual
Hardware Description
H
Channels
gives an overview of the receive buffer operating mode.
Channel Translation Modes (DS1/J1)
Channel
Translation
Mode 1
FS/DL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Time Slots
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
135
Channel
Translation
Mode 0
–
13
14
15
–
16
17
18
–
19
20
21
–
22
23
24
Channels
Functional Description T1/J1
Channel
Translation
Mode 1
16
17
18
19
20
21
22
23
24
–
–
–
–
–
–
–
DS1.1, 2003-10-23
PEF 2256 H/E
Time Slots
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
FALC
®
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