PEF2256 INFINEON [Infineon Technologies AG], PEF2256 Datasheet - Page 372

• Manufacturer Part Number: PEF2256
• Description: E1/T1/J1 Framer and Line Interface Component for Long- and Short-Haul Applications
• Manufacturer: INFINEON [Infineon Technologies AG]

Transmit Control 1 (Read/Write)
Value after reset: 9C
XC1
XCO(7:0)
User’s Manual
Hardware Description
XCO7
7
A write access to this address resets the transmit elastic buffer to its
basic starting position. Therefore, updating the value should only be
done when the FALC
centered. As a consequence a transmit slip will occur.
Transmit Offset
Initial value loaded into the transmit bit counter at the trigger edge of
SCLKX when the synchronous pulse on port SYPX/XMFS is active.
Calculation of delay time T (SCLKX cycles) depends on the value X
of the transmit offset register XC(1:0):
system clocking rate: modulo 2.048 MHz (SIC2.SSC2 = 0)
0 T 4: X = 4 - T
5 T maximum delay: X = 256
with maximum delay = (256
with SC = system clock defined by SIC1.SSC(1:0)+SIC2.SSC2
with SD = 2.048 Mbit/s (system clocking n
or
system clocking rate: modulo 1.544 MHz (SIC2.SSC2 = 1)
0 T 4: X = 3 - T + 7
5 T maximum delay: X = 200
with SC = system clock defined by SIC1.SSC(1:0)+SIC2.SSC2
SD = 1.544 Mbit/s (system clocking n
with BF = basic frequency = 1.544 MHz
T = Time between the active edge of SCLKX after SYPX pulse begin
and beginning of the next frame (F-bit, channel phase 0), measured
in number of SCLKX clock intervals; maximum delay:
T
See
max
H
page 185
= (200
SC/BF) - (7
for further description.
®
56 is initialized or when the buffer should be
372
SC/BF
SC/BF) - 1
SC/SD) -1
SC/SD - T + 4)
SC/BF - T + 3
1.544 MHz)
2.048 MHz)
DS1.1, 2003-10-23
T1/J1 Registers
PEF 2256 H/E
XCO0
0
FALC
(23)
®
56