PEF2256 INFINEON [Infineon Technologies AG], PEF2256 Datasheet - Page 301
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PEF2256
Manufacturer Part Number
PEF2256
Description
E1/T1/J1 Framer and Line Interface Component for Long- and Short-Haul Applications
Manufacturer
INFINEON [Infineon Technologies AG]
Datasheet
1.PEF2256.pdf
(518 pages)
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Table 65
Address
9B
9C
9D
9E
9F
A9
AA
AB
9.4
Receive FIFO - HDLC Channel 1 (Read)
RFIFO
RFIFO
Reading data from RFIFO of HDLC channel 1 can be done in an 8-bit (byte) or 16-bit
(word) access depending on the selected bus interface mode. The LSB is received first
from the serial interface.
The size of the accessible part of RFIFO is determined by programming the bits
CCR1.RFT(1:0) (RFIFO threshold level). It can be reduced from 32 bytes (reset value)
down to 2 bytes (four values: 32, 16, 4, 2 bytes).
Data Transfer
Up to 32 bytes/16 words of received data can be read from the RFIFO following an RPF
or an RME interrupt.
RPF Interrupt: A fixed number of bytes/words to be read (32, 16, 4, 2 bytes). The
message is not yet complete.
RME Interrupt: The message is completely received. The number of valid bytes is
determined by reading the RBCL, RBCH registers.
RFIFO is released by issuing the RMC (Receive Message Complete) command.
User’s Manual
Hardware Description
RF15
RF7
Detailed Description of E1 Status Registers
7
E1 Status Register Address Arrangement (cont’d)
Register
RSIS3
RFIFO2
RFIFO2
RFIFO3
RFIFO3
SIS2
RSIS2
MFPI
Type Comment
R
R
R
R
R
R
R
R
301
Receive Signaling Status Register 3
Receive FIFO 2
Receive FIFO 2
Receive FIFO 3
Receive FIFO 3
Signaling Status Register 2
Receive Signaling Status Register 2
MultiFunction Port Input Status
DS1.1, 2003-10-23
PEF 2256 H/E
RF0
RF8
E1 Registers
0
FALC
Page
341
343
343
343
343
337
339
343
(00)
(01)
®
56
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