PEF2256 INFINEON [Infineon Technologies AG], PEF2256 Datasheet - Page 179

• Manufacturer Part Number: PEF2256
• Description: E1/T1/J1 Framer and Line Interface Component for Long- and Short-Haul Applications
• Manufacturer: INFINEON [Infineon Technologies AG]

Figure 66
5.5.2
Compared to the receive paths the inverse functions are performed for the transmit
direction.
The interface to the transmit system highway is realized by two data buses, one for the
data XDI and one for the signaling data XSIG. The time slot assignment is equivalent to
the receive direction. All unequipped (idle) time slots are ignored.
Latching of data is controlled by the system clock (SCLKX or SCLKR) and the
synchronization pulse (SYPX/XMFS) in combination with the programmed offset values
for the transmit time slot/clock slot counters XC1/0. The frequency of the working clock
2.048/4.096/8.192/16.384 MHz or 1.544/3.088/6.176/12.352 MHz for the transmit
system interface is programmable by SIC1.SSC1/0 and SIC2.SSC2. Refer also
Table
The received bit stream on ports XDI and XSIG can be multiplexed internally on a time
slot basis, if enabled by SIC3.TTRF = 1. The data received on port XSIG can be sampled
if the transmit signaling marker XSIGM is active high. Data on port XDI is sampled if
XSIGM is low for the corresponding time slot. Programming the XSIGM marker is done
with registers TTR(4:1).
Note: XSIG is required in the last frame of a multiframe only and ignored in all other
User’s Manual
Hardware Description
SYPR
SCLKR
RDO
RSIG
RSIG
frames.
45.
T
F
ABCD, ABAB
Transmit System Interface (T1/J1)
A B C D
A B A B
4 5 6 7
TS23
1.544 MHz Receive Signaling Highway (T1/J1)
T
F
F
F
0 1 2 3 4 5 6 7
= Time slot offset (RC0, RC1)
= FS/DL-bit
= Signaling bits for time slots 1...23
TS0
A B C D
A B A B
0 1 2 3 4 5 6 7
TS1
A B C D
A B A B
125 µs
179
Functional Description T1/J1
0 1 2 3 4 5 6 7
TS23
DS1.1, 2003-10-23
PEF 2256 H/E
A B C D
A B A B
FALC
F0134
F
F
F
ESF
F12
®
56