PEF2256 INFINEON [Infineon Technologies AG], PEF2256 Datasheet - Page 271

• Manufacturer Part Number: PEF2256
• Description: E1/T1/J1 Framer and Line Interface Component for Long- and Short-Haul Applications
• Manufacturer: INFINEON [Infineon Technologies AG]

DCF
IRSP
IRSC
User’s Manual
Hardware Description
DCO-R Center- Frequency Disabled
0 =
1 =
Internal Receive System Frame Sync Pulse
0 =
1 =
Internal Receive System Clock
0 =
1 =
The DCO-R circuitry is frequency centered
- in master mode if no 2.048 MHz reference clock on pin SYNC
is provided or
- in slave mode if a loss-of-signal occurs in combination with no
2.048 MHz clock on pin SYNC or
- a gapped clock is provided on pin RCLKI and this clock is
inactive or stopped.
The center function of the DCO-R circuitry is disabled. The
generated clock (DCO-R) is frequency frozen in that moment
when no clock is available on pin SYNC or pin RCLKI. The
DCO-R circuitry starts synchronization as soon as a clock
appears on pins SYNC or RCLKI.
The frame sync pulse for the receive system interface is
sourced by SYPR (if SYPR is applied). If SYPR is not applied,
the frame sync pulse is derived from RDO output signal
internally free running).
The use of IRSP = 0 is recommended.
The frame sync pulse for the receive system interface is
internally sourced by the DCO-R circuitry. This internally
generated frame sync signal can be output (active low) on
multifunction ports RP(A to D) (RPC(2:0) = 001
Note: This is the only exception where the use of RFM and
SYPR is allowed at the same time. Because only one set of
offset registers (RC1/0) is available, programming is done by
using the SYPR calculation formula in the same way as for the
external SYPR pulse. Bit IRSC must be set for correct
operation.
The working clock for the receive system interface is sourced
by SCLKR or in receive elastic buffer bypass mode from the
corresponding extracted receive clock RCLK.
The working clock for the receive system interface is sourced
internally by DCO-R or in bypass mode by the extracted receive
clock. SCLKR is ignored.
271
DS1.1, 2003-10-23
PEF 2256 H/E
B
).
E1 Registers
FALC
®
56