PEF2256 INFINEON [Infineon Technologies AG], PEF2256 Datasheet - Page 230

• Manufacturer Part Number: PEF2256
• Description: E1/T1/J1 Framer and Line Interface Component for Long- and Short-Haul Applications
• Manufacturer: INFINEON [Infineon Technologies AG]

HDLCI
Receive Address Byte High Register 1 (Read/Write)
Value after reset: FD
RAH1
In operating modes that provide high byte address recognition, the high byte of the
received address is compared to the individually programmable values in RAH1 and
RAH2. The address registers are used by all HDLC channels in common.
RAH1
Receive Address Byte High Register 2 (Read/Write)
Value after reset: FF
RAH2
RAH2
Receive Address Byte Low Register 1 (Read/Write)
Value after reset: FF
RAL1
RAL1
User’s Manual
Hardware Description
7
7
7
Value of Second Individual High Address Byte
Inverse HDLC Operation - HDLC Channel 1
Setting this bit selects the HDLC channel 1 operation mode.
0
1
Value of the First Individual High Address Byte
Bit 1 (C/R-bit) is excluded from address comparison.
Value of First Individual Low Address Byte
H
H
H
Normal operation, HDLC attached to line side
Inverse operation, HDLC attached to system side and receive
line HDLC data is ignored. HDLC data is received on XDI and
stored in RFIFO and is transmitted from XFIFO to RDO.
Transmit time slot configuration is done in RTR(4:1), receive
time slot configurarion is done in TTR(4:1).
230
0
DS1.1, 2003-10-23
PEF 2256 H/E
E1 Registers
0
0
0
FALC
(04)
(05)
(06)
®
56