PEF2256 INFINEON [Infineon Technologies AG], PEF2256 Datasheet - Page 400

• Manufacturer Part Number: PEF2256
• Description: E1/T1/J1 Framer and Line Interface Component for Long- and Short-Haul Applications
• Manufacturer: INFINEON [Infineon Technologies AG]

Errored Second Mask (Read/Write)
Value after reset: FF
ESM
ESM
Clock Mode Register 3 (Read/Write)
Value after reset: 00
CMR3
Table 69
CFAX(3:0)
7
3
Disable Error Counter (Write)
Value after reset: 00
DEC
DRBD
DCOEC
DBEC
User’s Manual
Hardware Description
DRBD
LFA
7
7
7
DCO-R and DCO-X Corner Frequency Programing (T1/J1)
Disable COFA Event Counter
Errored Second Mask
This register functions as an additional mask register for the interrupt
status bit Errored Second (ISR3.ES). A "1" in a bit position of ESM
deactivates the related second interrupt.
Disable Receive Buffer Delay
This bit has to be set before reading the register RBD. It is
automatically reset if RBD has been read.
Disable PRBS Bit Error Counter
Only valid if LCR1.EPRM = 1 and FMR1.ECM are reset.
FER
H
H
H
CFAX(3:0)
DCO-X Corner
Frequency [Hz]
0.6
6.0
DCOEC
CER
DBEC
AIS
400
CFAR(3:0)
7
3
DCEC
LOS
DEBC
CVE
CFAR(3:0)
DCVC
SLIP
DCO-R Corner
Frequency [Hz]
0.6
6.0
DS1.1, 2003-10-23
T1/J1 Registers
PEF 2256 H/E
DFEC
0
0
0
FALC
(47)
(48)
(60)
®
56