PEF2256 INFINEON [Infineon Technologies AG], PEF2256 Datasheet - Page 159

• Manufacturer Part Number: PEF2256
• Description: E1/T1/J1 Framer and Line Interface Component for Long- and Short-Haul Applications
• Manufacturer: INFINEON [Infineon Technologies AG]

5.3.9
The FALC
is defined by ANSI T1. 403. More than 14 consecutive zeros or less than N ones in each
and every time window of 8 (N+1) data bits where N = 23 are detected. Violations of
these rules are indicated by setting the status bit FRS1.PDEN and the interrupt status bit
ISR0.PDEN. Generation of the interrupt status is programmed either with the detection
or with any change of state of the pulse-density alarm (GCR.SCI).
5.4
5.4.1
The serial bit stream is then processed by the transmitter which has the following
functions:
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The frame/multiframe boundaries of the transmitter can be synchronized externally by
using the SYPX/XMFS pin. Any change of the transmit time slot assignment
subsequently produces a change of the framing bit positions on the line side. This
feature is required if signaling and data link bits are routed through the switching network
and are inserted in transmit direction by the system interface.
In loop-timed configuration (LIM2.ELT) disconnecting the control of the transmit system
highway from the transmitter is done by setting FMR5.XTM. The transmitter is now in a
free running mode without any possibility to update the multiframe position in case of
changing the transmit time slot assignment. The FS/DL-bits are generated independent
of the transmit system interface. For proper operation the transmit elastic buffer size
should be programmed to 2 frames.
The contents of selectable time slots is overwritten by the pattern defined by register
IDLE. The selection of “idle channels” is done by programming the three-byte registers
ICB(3:1).
If AMI coding with zero code suppression (B7-stuffing) is selected, “clear channels”
without B7-stuffing can be defined by programming registers CCB(3:1).
User’s Manual
Hardware Description
Frame/multiframe synthesis of one of the four selectable framing formats
Insertion of service and data link information
AIS generation (blue alarm)
Remote alarm (yellow alarm) generation
CRC generation and insertion of CRC bits
CRC bits inversion in case of a previously received CRC error or in case of activating
per control bit
Generation of loop-up/-down code
Idle code generation per DS0
®
56 examines the receive data stream on the pulse-density requirement which
Pulse-Density Detection
Transmit Path in T1/J1 Mode
Transmitter (T1/J1)
159
Functional Description T1/J1
DS1.1, 2003-10-23
PEF 2256 H/E
FALC
®
56