PEF2256 INFINEON [Infineon Technologies AG], PEF2256 Datasheet - Page 262

• Manufacturer Part Number: PEF2256
• Description: E1/T1/J1 Framer and Line Interface Component for Long- and Short-Haul Applications
• Manufacturer: INFINEON [Infineon Technologies AG]

EOU
Loop Code Register 1 (Read/Write)
Value after reset: 00
LCR1
EPRM
XPRBS
LDC(1:0)
User’s Manual
Hardware Description
EPRM
7
XPRBS
E1 Pulse Mask Undershoot
This bit controls the transmit pulse template during the 2nd half of the
pulse. If enabled, the values programmed in XP3 and XP4 are used
to generate a pulse undershoot. This can be used to achieve faster
slew rates.
0 =
1 =
Enable Pseudo-Random Binary Sequence Monitor
0 =
1 =
Transmit Pseudo-Random Binary Sequence
A one in this bit position enables transmission of a pseudo-random
binary sequence to the remote end. Depending on bit LLBP the PRBS
is generated according to 2
restriction (ITU-T O. 151).
Length Deactivate (Down) Code
These bits defines the length of the LLB deactivate code which is
programmable in register LCR2.
00 = Length: 5 bit
01 = Length: 6 bit, 2 bit, 3 bit
10 = Length: 7 bit
11 = Length: 8 bit, 2 bit, 4bit
H
XP3/XP4 are used as positive values.
XP3/XP4 are used as negative values.
Pseudo-Random Binary Sequence (PRBS) monitor is disabled.
PRBS is enabled. Setting this bit enables incrementing the
CEC2 error counter with each detected PRBS bit error. With
any change of state of the PRBS internal synchronization
status an interrupt ISR1.LLBSC is generated. The current
status of the PRBS synchronizer is indicated by bit
RSP.LLBAD.
LDC1
LDC0
262
LAC1
15
-1 or 2
LAC0
20
-1 with a maximum-14-zero
FLLB
DS1.1, 2003-10-23
PEF 2256 H/E
LLBP
E1 Registers
0
FALC
(3B)
®
56