PEF2256 INFINEON [Infineon Technologies AG], PEF2256 Datasheet - Page 414

• Manufacturer Part Number: PEF2256
• Description: E1/T1/J1 Framer and Line Interface Component for Long- and Short-Haul Applications
• Manufacturer: INFINEON [Infineon Technologies AG]

CSF
AFX
CR
EPR
Mode Register 2 (Read/Write)
Value after reset: 00
MODE2
MDS2(2:0)
User’s Manual
Hardware Description
MDS22
7
MDS21
Compare Status Field - HDLC Channel 1
If the status fields of consecutive LSSUs are equal, only the first is
stored and every following is ignored.
0 =
1 =
Automatic FISU Transmission - HDLC Channel 1
After the contents of the transmit FIFO (XFIFO) has been transmitted
completely, FISUs are transmitted automatically. These FISUs
contain the FSN and BSO of the last transmitted signaling unit
(provided in XFIFO).
0 =
1 =
Command Response - HDLC Channel 1
Reflects the status of the CR bit in the SAPI octet transmitted during
Periodical Performance Report (PPR), if CCR5.EPR = 1.
0 =
1 =
Enable Periodical Performance Report (PPR) - HDLC Channel 1
If the periodical performance report is to be used, an HDLC format
must be selected by MODE.MDS(2:0).
0 =
1 =
Mode Select - HDLC Channel 2
The operating mode of the HDLC controller is selected.
000 Reserved
001 Reserved
010 One-byte address comparison mode (RAL1, 2)
011 Two-byte address comparison mode (RAH1, 2 and RAL1, 2)
H
PPR disabled.
PPR enabled.
Compare disabled.
Compare enabled.
Automatic FISU transmission disabled.
Automatic FISU transmission enabled.
CR bit = 0
CR bit = 1
MDS20
414
HRAC2
DIV2
DS1.1, 2003-10-23
T1/J1 Registers
PEF 2256 H/E
0
FALC
(8E)
®
56