PEF2256 INFINEON [Infineon Technologies AG], PEF2256 Datasheet - Page 47

• Manufacturer Part Number: PEF2256
• Description: E1/T1/J1 Framer and Line Interface Component for Long- and Short-Haul Applications
• Manufacturer: INFINEON [Infineon Technologies AG]

Table 5
Pin (Ball)
No.
1 (A1)
8 (D1)
10 (E4)
10 (B9)
25 (C5)
35 (E4)
42 (H9)
59 (J3)
72 (J7)
Analog Switch
19 (H1)
20 (H2)
Device Reset
13 (F3)
JTAG Test Interface
14 (F1)
15 (G1)
16 (F2)
User’s Manual
Hardware Description
Name
V
RES
TMS
AS1
AS2
TRS
TDI
SS
Miscellaneous Pin Definitions (cont’d)
Pin
Type
S
I/O
I/O
I
I
I
I
Buffer
Type
analog Analog Switch
analog
PU
PU
PU
Function
Ground
All analog and digital circuits are connected to
a common ground within the device package.
These pins provide the terminals for an
analog switch to be used in redundancy
applications.
Hardware Reset
During reset the FALC
clock on pin MCLK. During reset all
bidirectional output stages are in input mode,
if signal RD is “high” (which disables the data
bus D(15:0) output drivers).
0
1
Test Access Port (TAP) Reset
Initializes the boundary scan test logic. If the
boundary scan logic is not used, this pin must
be connected to RST or VSS
0
1
Test Data Input
Boundary scan input signal.
Test Mode Select
Boundary scan test mode select.
47
B
B
B
B
RES_0, device reset.
RES_1, operational mode.
TRS_0, TAP controller reset.
TRS_1, TAP operational mode.
®
56 needs an active
External Signals
DS1.1, 2003-10-23
PEF 2256 H/E
FALC
®
56