PEF2256 INFINEON [Infineon Technologies AG], PEF2256 Datasheet - Page 360

• Manufacturer Part Number: PEF2256
• Description: E1/T1/J1 Framer and Line Interface Component for Long- and Short-Haul Applications
• Manufacturer: INFINEON [Infineon Technologies AG]

Single Bit Defect Insertion Register (Read/Write)
Value after reset: 00
IERR
After setting the corresponding bit, the selected defect is inserted into the transmit data
stream at the next possible position. After defect insertion is completed, the bit is reset
automatically.
IFASE
IMFE
ICRCE
ICASE
IPE
IBV
Framer Mode Register 0 (Read/Write)
Value after reset: 00
FMR0
XC(1:0)
RC(1:0)
User’s Manual
Hardware Description
XC1
7
Note: Except for CRC defects, CRC checksum calculation is done
Serial line code for the transmitter, independent of the receiver.
Serial code receiver is independent to the transmitter.
Insert single FAS defect
Insert single multiframe defect
Insert single CRC defect
Insert single CAS defect
Insert single PRBS defect
Insert bipolar violation
Transmit Code
00 = NRZ (optical interface)
01 = CMI (1T2B+B8ZS), (optical interface)
10 = AMI coding with Zero Code Suppression (ZCS, B7-stuffing).
11 = B8ZS Code (ternary or digital dual-rail interface).
After changing XC(1:0), a transmitter software reset is required
(CMDR.XRES = 1).
Receive Code
XC0
H
H
after defect insertion.
Disabling of the ZCS is done by activating the clear channel
mode by register CCB(3:1). (ternary or digital interface)
IFASE
RC1
IMFE
RC0
360
ICRCE
FRS
ICASE
SRAF
EXLS
IPE
DS1.1, 2003-10-23
T1/J1 Registers
PEF 2256 H/E
SIM
IBV
0
FALC
(1B)
(1C)
®
56