PEF2256 INFINEON [Infineon Technologies AG], PEF2256 Datasheet - Page 250

• Manufacturer Part Number: PEF2256
• Description: E1/T1/J1 Framer and Line Interface Component for Long- and Short-Haul Applications
• Manufacturer: INFINEON [Infineon Technologies AG]

User’s Manual
Hardware Description
Delay time T = time between beginning of time slot 0 at RDO and the
initial edge of SCLKR after SYPR goes active.
See
Receive Frame Marker Offset (PC(4:1).RPC(2:0) = 001
Offset programming of the receive frame marker which is output on
multifunction port RFM. The receive frame marker can be activated
during any bit position of the entire frame and depends on the
selected system clock rate.
Calculation of the value X of the receive offset register RC(1:0)
depends on the bit position which should be marked at marker
position MP:
0 MP 2045:X = MP + 2
2046 MP 2047: X = MP - 2046
e.g: 2.048 MHz: MP = 0 to 255; up to 16.384 MHz: MP = 0 to 2047
page 109
for further description.
250
DS1.1, 2003-10-23
PEF 2256 H/E
E1 Registers
B
FALC
)
®
56