PEF2256 INFINEON [Infineon Technologies AG], PEF2256 Datasheet - Page 207

• Manufacturer Part Number: PEF2256
• Description: E1/T1/J1 Framer and Line Interface Component for Long- and Short-Haul Applications
• Manufacturer: INFINEON [Infineon Technologies AG]

Specific T1/J1 Initialization
The following is a suggestion for a basic initialization to meet most of the T1/J1
requirements. Depending on different applications and requirements any other
initialization can be used.
Table 56
Register
FMR0.XC0/1
FMR0.RC0/1
LIM1.DRS
CCB(3:1)
SIC3.CMI
PCD = 0A
PCR = 15
LIM1.RIL(2:0)
GCR.SCI = 1
LIM2.LOS1 = 1
User’s Manual
Hardware Description
= 02
H
H
H
Line Interface Initialization (T1/J1)
Function
The FALC
interface as well as the digital line interface. For the analog line
interface the codes AMI (with and without bit 7stuffing) and
B8ZS are supported. For the digital line interface modes (dual-
or single-rail) the FALC
stuffing), B8ZS (with and without B8ZS precoding) and NRZ.
LOS detection after 176 consecutive “zeros” (fulfills G.775/
Telcordia (Bellcore)/AT&T)
LOS recovery after 22 “ones” in the PCD interval (fulfills G.775,
Bellcore/AT&T).
LOS threshold of 0.6 V (fulfills G.775).
Additional Recovery Interrupts. Help to meet alarm activation
and deactivation conditions in time.
Automatic pulse-density check on 15 consecutive zeros for LOS
recovery condition (Bellcore requirement)
®
56 supports requirements for the analog line
207
®
56 supports AMI (with and without bit 7
Operational Description T1/J1
DS1.1, 2003-10-23
PEF 2256 H/E
FALC
®
56