PEF2256 INFINEON [Infineon Technologies AG], PEF2256 Datasheet - Page 54

• Manufacturer Part Number: PEF2256
• Description: E1/T1/J1 Framer and Line Interface Component for Long- and Short-Haul Applications
• Manufacturer: INFINEON [Infineon Technologies AG]

3.3.1.3
Special events in the FALC
programmable characteristics (open drain or push-pull, defined by register IPC), which
requests the CPU to read status information from the FALC
from/to the FALC
Since only one INT request output is provided, the cause of an interrupt must be
determined by the CPU by reading the FALC
ISR(5:0)). The interrupt on pin INT and the interrupt status bits are reset by reading the
interrupt status registers. Register ISR(5:0) are of type “clear on read“.
The structure of the interrupt status registers is shown in
Figure 8
Each interrupt indication of registers ISR(5:0) can be selectively masked by setting the
according bit in the corresponding mask registers IMR(5:0). If the interrupt status bits are
masked they neither generate an interrupt at INT nor are they visible in ISR(5:0).
GIS, the non-maskable Global Interrupt Status Register, serves as pointer to pending
interrupts. After the FALC
CPU should first read the Global Interrupt Status register GIS to identify the requesting
User’s Manual
Hardware Description
Global
Interrupt
Status
Register GIS
Interrupt Interface
Interrupt Status Registers
®
56.
ISR0
ISR1
ISR2
ISR3
ISR4
ISR5
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56 has requested an interrupt by activating its INT pin, the
®
56 are indicated by means of a single interrupt output with
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ISR0
ISR2
ISR4
IMR0
IMR2
IMR4
®
56’s interrupt status registers (GIS,
Functional Description E1/T1/J1
Figure
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56, or to transfer data
8.
ISR1
ISR3
ISR5
DS1.1, 2003-10-23
PEF 2256 H/E
IMR1
IMR3
IMR5
F0127 V1.0
FALC
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