PEF2256 INFINEON [Infineon Technologies AG], PEF2256 Datasheet - Page 206

• Manufacturer Part Number: PEF2256
• Description: E1/T1/J1 Framer and Line Interface Component for Long- and Short-Haul Applications
• Manufacturer: INFINEON [Infineon Technologies AG]

consequent actions to remote end and internal system depend on the activation
procedure selected.
Table 55
Basic Set Up
Master clocking mode
T1/J1 mode select
Specification of line
interface and clock
generation
Line interface coding
Loss-of-signal detection/
recovery conditions
System clocking and data
rate
Channel translation mode
Transmit offset counters
Receive offset counters
AIS to system interface
Operational Setup
Select framing
Framing additions
Synchronization mode
Signaling mode
Note: Read access to unused register addresses: value should be ignored.
User’s Manual
Hardware Description
Write access to unused register addresses: should be avoided, or set to 00
address range up to AF
defined elsewhere.
All control registers (except XFIFO, XS(12:1), CMDR, DEC) are of type read/write
Initialization Parameters (T1/J1)
T1
GCM(8:1) according to external MCLK clock frequency
FMR1.PMOD = 1,
RC0.SJR = 0
LIM0, LIM1, XPM(2:0)
FMR0.XC(1:0), FMR0.RC(1:0)
PCD, PCR, LIM1, LIM2
SIC1.SSC(1:0), SIC1.SSD1, FMR1.SSD0, CMR1.IRSP/
IRSC/IXSP/IXSC
XC0.XCO, XC1.XTO
RC0.RCO, RC1.RTO
FMR4.FM(1:0)
FMR1.CRC, FMR0.SRAF
FMR4.AUTO, FMR4.SSC(1:0), FMR2.MCSP,
FMR2.SSP
FMR5.EIBR, XC0.BRM, MODE, MODE2, MODE3,
CCR1, CCR2, RAH(2:1), RAL(2:1)
FMR1.CTM
FMR2.DAIS/SAIS
H
; must be avoided in address range above AF
206
Operational Description T1/J1
J1
FMR1.PMOD = 1,
RC0.SJR = 1
DS1.1, 2003-10-23
PEF 2256 H/E
FALC
H
if not
®
H
56
in