PEF2256 INFINEON [Infineon Technologies AG], PEF2256 Datasheet - Page 359
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PEF2256
Manufacturer Part Number
PEF2256
Description
E1/T1/J1 Framer and Line Interface Component for Long- and Short-Haul Applications
Manufacturer
INFINEON [Infineon Technologies AG]
Datasheet
1.PEF2256.pdf
(518 pages)
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Interrupt Mask Registers
Value after reset: FF
IMR0
IMR1
IMR2
IMR3
IMR4
IMR5
IMR(5:0)
User’s Manual
Hardware Description
CASE
XPR2
RME
FAR
XSP
ES
7
Interrupt Mask Register
Each interrupt source can generate an interrupt signal on port INT
(characteristics of the output stage are defined by register IPC). A “1”
in a bit position of IMR(5:0) sets the mask active for the interrupt
status in ISR(5:0). Masked interrupt statuses neither generate a
signal on INT, nor are they visible in register GIS. Moreover, they are
– not displayed in the Interrupt Status Register if bit GCR.VIS is
– displayed in the Interrupt Status Register if bit GCR.VIS is set
After reset, all interrupts are disabled.
XPR3
RDO
SEC
XSN
RFS
LFA
H
, FF
cleared
H
, FF
MFAR
RME2
RME3
ALLS
ISF
H
, FF
H
LMFA
RFS2
RFS3
RMB
,FF
XDU
H
359
LLBSC
RDO2
RDO3
XMB
RSC
AIS
ALLS2
ALLS3
CRC6
SUEX
LOS
PDEN
XLSC
XDU2
XDU3
RAR
RSN
DS1.1, 2003-10-23
T1/J1 Registers
PEF 2256 H/E
RPF2
RPF3
RPF
XPR
RSP
RA
0
FALC
(14)
(15)
(16)
(17)
(18)
(19)
®
56
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