PEF2256 INFINEON [Infineon Technologies AG], PEF2256 Datasheet - Page 348

• Manufacturer Part Number: PEF2256
• Description: E1/T1/J1 Framer and Line Interface Component for Long- and Short-Haul Applications
• Manufacturer: INFINEON [Infineon Technologies AG]

Note: Read access to unused register addresses: value should be ignored.
10.2
Transmit FIFO - HDLC Channel 1 (Write)
XFIFO
XFIFO
Writing data to XFIFO of HDLC channel 1 can be done in 8-bit (byte) or 16-bit (word)
access. The LSB is transmitted first.
Up to 32 bytes/16 words of transmit data can be written to the XFIFO following an XPR
interrupt.
Command Register (Write)
Value after reset: 00
CMDR
RMC
RRES
XREP
User’s Manual
Hardware Description
Write access to unused register addresses: should be avoided, or set to 00
address range up to AF
defined elsewhere.
XF15
RMC
XF7
Detailed Description of T1/J1 Control Registers
7
7
Receive Message Complete - HDLC Channel 1
Confirmation from CPU to FALC
block has been fetched following an RPF or RME interrupt, thus the
occupied space in the RFIFO can be released. If RMC is given while
RFIFO is already cleared, the next incoming data block is cleared
instantly, although interrupts are generated.
Receiver Reset
The receive line interface except the clock and data recovery unit
(DPLL), the receive framer, the one-second timer and the receive
signaling controller are reset. However the contents of the control
registers is not deleted.
Transmission Repeat - HDLC Channel 1
RRES
H
XREP
H
; must be avoided in address range above AF
XRES
348
XHF
®
56 that the current frame or data
XTF
XME
DS1.1, 2003-10-23
T1/J1 Registers
PEF 2256 H/E
SRES
XF0
XF8
0
0
FALC
H
(00)
(01)
(02)
if not
®
H
56
in