PEF2256 INFINEON [Infineon Technologies AG], PEF2256 Datasheet - Page 97

• Manufacturer Part Number: PEF2256
• Description: E1/T1/J1 Framer and Line Interface Component for Long- and Short-Haul Applications
• Manufacturer: INFINEON [Infineon Technologies AG]

4.4
4.4.1
The serial bit stream is processed by the transmitter which has the following functions:
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The frame/multiframe boundaries of the transmitter can be externally synchronized by
using the SYPX/XMFS pin. Any change of the transmit time slot assignment
subsequently produces a change in the framing bit positions on the line side. This feature
is required if signaling and service bits are routed through the switching network and are
inserted in transmit direction by the system interface.
In loop-timed configuration (LIM2.ELT = 1) disconnecting the control of the transmit
system highway from the transmitter is done by setting XSW.XTM. The transmitter is
now in a free running mode without any possibility to update the multiframe position in
case of changing the transmit time slot assignment. The framing bits are generated
independently of the transmit system interface. For proper operation the transmit elastic
buffer size should be programmed to 2 frames.
The contents of selectable time slots can be overwritten by the pattern defined by
register IDLE. The selection of “idle channels” is done by programming the four-byte
registers ICB1…ICB4.
User’s Manual
Hardware Description
Frame/multiframe synthesis of one of the two selectable framing formats
Insertion of service and data link information
AIS generation (Alarm indication signal)
Remote alarm generation
CRC generation and insertion of CRC bits
CRC bits inversion in case of a previously received CRC error
Idle code generation per DS0
Transmit Path in E1 Mode
Transmitter (E1)
97
Functional Description E1
DS1.1, 2003-10-23
PEF 2256 H/E
FALC
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