PEF2256 INFINEON [Infineon Technologies AG], PEF2256 Datasheet - Page 38

• Manufacturer Part Number: PEF2256
• Description: E1/T1/J1 Framer and Line Interface Component for Long- and Short-Haul Applications
• Manufacturer: INFINEON [Infineon Technologies AG]

Table 4
Pin or
Ball No.
66 (B6)
65 (A7)
User’s Manual
Hardware Description
Name
RDO
SCLKR
Pin Definitions - System Interface
Pin
Type
O
I/O
Buffer
Type
PU
Function
Receive Data Output
Received data that is sent to the system
highway. Clocking of data is done with the
rising or falling edge (SIC3.RESR) of SCLKR
or RCLK, if the receive elastic store is
bypassed. The delay between the beginning
of time slot 0 and the initial edge of SCLKR
(after SYPR goes active) is determined by the
values of registers RC1 and RC0. If received
data is shifted out with higher data rates
(more than 2.048/1.544 Mbit/s), the active
channel phase is defined by bits
SIC2.SICS(2:0). During inactive channel
phases RDO is cleared (driven to low level or
tristate, see SIC3.RTRI on page 267/393).
Receive System Clock
Working clock for the receive system
interface with a frequency of
16.384/8.192/4.096/2.048 MHz in E1 mode
and 16.384/8.192/4.096/2.048 MHz
(SIC2.SSC2 = 0
12.352/6.176/3.088/1.544 MHz
(SIC2.SSC2 = 1
receive elastic store is bypassed, the clock
supplied on this pin is ignored, because
RCLK is used to clock the receive system
interface. If SCLKR is configured to be an
output, the internal working clock of the
receive system interface sourced by DCO-R
or RCLK is output.
38
B
B
) or
) in T1/J1 mode. If the
External Signals
DS1.1, 2003-10-23
PEF 2256 H/E
FALC
®
56