PEF2256 INFINEON [Infineon Technologies AG], PEF2256 Datasheet - Page 151
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PEF2256
Manufacturer Part Number
PEF2256
Description
E1/T1/J1 Framer and Line Interface Component for Long- and Short-Haul Applications
Manufacturer
INFINEON [Infineon Technologies AG]
Datasheet
1.PEF2256.pdf
(518 pages)
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•
Setting of RC0.SJR the FALC
JT G.706. The CRC6 checksum is calculated including the FS/DL-bits. In synchronous
state CRC6 errors increment an error counter.
5.2.7
The 72-multiframe is an alternate use of the FS-bit pattern and is used for carrying data
link information. This is done by stealing some of redundant multiframing bits after the
transmission of the 12-bit framing header (refer to
of A and B signaling channels (robbed bit signaling) is defined by zero-to-one and
one-to-zero transitions of the FS-bits and is continued when the FS-bits are replaced by
the data link bits.
Remote alarm (yellow alarm) is indicated by setting bit 2 to zero in each time slot. An
additional use of the D-bits for alarm indication is user defined and must be done
externally.
5.2.7.1
In the synchronous state terminal framing (FT-bits) and multiframing (FS-bits of the
framing header) are observed independently. Further reaction on framing errors
depends on the selected synchronization/resynchronization procedure (by bit
FMR2.SSP):
•
•
User’s Manual
Hardware Description
CRC6 generation/checking according to JT G.706
FMR2.SSP = 0: terminal frame and multiframe synchronization are combined
Two errors within 4/5/6 framing bits (by bits FMR4.SSC1/0) of one of the above lead
to the asynchronous state for terminal framing and multiframing. Additionally to The
resynchronization procedure starts with synchronizing upon the terminal framing. If
the pulse framing has been regained, the search for multiframe alignment is initiated.
Multiframe synchronization has been regained after two consecutive correct
multiframe patterns have been received.
FMR2.SSP = 1: terminal frame and multiframe synchronization are separated
Two errors within 4/5/6 terminal framing bits lead to the same reaction as described
above for the “combined” mode.
Two errors within 4/5/6 multiframing bits lead to the asynchronous state only for the
multiframing. Loss of multiframe alignment is reported by bit FRS0.LMFA. The state
of terminal framing is not influenced.
Now, the resynchronization procedure includes only the search for multiframe
alignment. Multiframe synchronization has been regained after two consecutive
correct multiframe patterns have been received.
72-Frame Multiframe (SLC96 Format, T1/J1)
Synchronization Procedure
®
56 generates and checks the CRC6 bits according to
151
Figure 37
Functional Description T1/J1
on page 152). The position
DS1.1, 2003-10-23
PEF 2256 H/E
FALC
®
56
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