PEF2256 INFINEON [Infineon Technologies AG], PEF2256 Datasheet - Page 196

• Manufacturer Part Number: PEF2256
• Description: E1/T1/J1 Framer and Line Interface Component for Long- and Short-Haul Applications
• Manufacturer: INFINEON [Infineon Technologies AG]

Table 47
Register
LOOP
XSW
XSP
TSWM
XC0
XC1
RC0
RC1
IDLE
ICB(4:1)
LIM0
LIM1
PCD
PCR
XPM(2:0)
IMR(5:0)
RTR(4:1)
TTR(4:1)
TSS2
TSS3
GCR
CMR1
CMR2
MODE
MODE2
MODE3
RAH(2:1)
RAL(2:1)
User’s Manual
Hardware Description
Reset Value Meaning
00
00
00
00
00
9C
00
9C
00
00
00
00
00
00
40
FF
all 00
all 00
00
00
00
00
00
00
00
00
FD
FF
Initial Values after Reset (E1) (cont’d)
H
H
H
H
H
H
H
H
H
H
H
H
H,
H
H
H
H
H
H
H
H
H
H
H
H
H
, FF
, FF
03
H
H
H
H
, 7B
H
H
Channel loop-back and single frame mode are disabled.
All bits of the transmitted service word are cleared. Spare
bit values are cleared.
No transparent mode active.
The transmit clock offset is cleared.
The transmit time slot offset is cleared.
The receive clock slot offset is cleared.
The receive time slot offset is cleared.
Idle channel code is cleared.
Normal operation (no “Idle Channel” selected).
Slave Mode, local loop off
Analog interface selected, remote loop off
Pulse count for LOS detection cleared
Pulse count for LOS recovery cleared
Transmit pulse mask (transmitter in tristate mode)
All interrupts are disabled
No time slots selected
Internal second timer, power on
RCLK output: DPLL clock, DCO-X enabled, DCO-X
internal reference clock
SCLKR selected, SCLKX selected, receive
synchronization pulse sourced by SYPR, transmit
synchronization pulse sourced by SYPX
Signaling controller disabled
Compare register for receive address cleared
196
Operational Description E1
DS1.1, 2003-10-23
PEF 2256 H/E
FALC
®
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