PEF2256 INFINEON [Infineon Technologies AG], PEF2256 Datasheet - Page 441

• Manufacturer Part Number: PEF2256
• Description: E1/T1/J1 Framer and Line Interface Component for Long- and Short-Haul Applications
• Manufacturer: INFINEON [Infineon Technologies AG]

Signaling Status Register (Read)
SIS
XDOV
XFW
XREP
IVB
RLI
CEC
SFS
User’s Manual
Hardware Description
XDOV
7
Transmit Data Overflow - HDLC Channel 1
More than 32 bytes have been written to the XFIFO.
This bit is reset
– by a transmitter reset command XRES or
– when all bytes in the accessible half of the XFIFO have been moved
Transmit FIFO Write Enable - HDLC Channel 1
Data can be written to the XFIFO.
Transmission Repeat - HDLC Channel 1
Status indication of CMDR.XREP.
Invalid BOM Frame Received - HDLC Channel 1
0
1
Receive Line Inactive - HDLC Channel 1
Neither flags as interframe time fill nor frames are received in the
signaling time slot.
Command Executing
0
1
Note: CEC is active at most 2.5 periods of the current system data
Status Freeze Signaling
0 =
1 =
XFW
in the inaccessible half.
Valid BOM frame (11111111, 0xxxxxx0) received.
Invalid BOM frame received.
No command is currently executed, the CMDR register can be
written to.
A command (written previously to CMDR) is currently executed,
no further command can be temporarily written in CMDR
register.
rate.
Freeze signaling status inactive.
Freeze signaling status active.
XREP
IVB
441
RLI
CEC
SFS
DS1.1, 2003-10-23
T1/J1 Registers
PEF 2256 H/E
BOM
0
FALC
(64)
®
56