PEF2256 INFINEON [Infineon Technologies AG], PEF2256 Datasheet - Page 279

• Manufacturer Part Number: PEF2256
• Description: E1/T1/J1 Framer and Line Interface Component for Long- and Short-Haul Applications
• Manufacturer: INFINEON [Infineon Technologies AG]

User’s Manual
Hardware Description
0000 = SYPX: Synchronous Pulse Transmit (Input)
0001 = XMFS: Transmit Multiframe Synchronization (Input)
0010 = XSIG: Transmit Signaling Data (Input)
0011 = TCLK: Transmit Clock (Input)
0100 = XMFB: Transmit Multiframe Begin (Output)
0101 = XSIGM: Transmit Signaling Marker (Output)
0110 = DLX: Data Link Bit Transmit (Output)
0111 = XCLK: Transmit Line Clock (Output)
1000 = XLT: Transmit Line Tristate (Input)
1001 = GPI: General Purpose Input
1010 = GPOH: General Purpose Output High
1011 = GPOL: General Purpose Output Low
Together with register XC(1:0) SYPX defines the frame begin
on the transmit system interface ports XDI and XSIG.
Together with register XC(1:0) XMFS defines the frame and
multiframe begin on the transmit system interface ports XDI
and XSIG. Depending on PC5.CXMFS the signal on XMFS is
active high or low.
Input for transmit signaling data received from the signaling
highway. Optionally sampling of XSIG data is controlled by
the active high XSIGM marker.
A 2.048/8.192 MHz clock has to be sourced by the system if
the internal generated transmit clock (DCO-X) is not used.
Optionally this input is used as a synchronization clock for the
DCO-X circuitry with a frequency of 2.048 MHz.
Marks the beginning of every transmit multiframe.
Marks the time slots which are defined by register TTR(4:1) of
every frame on port XDI.
Marks the S
Frequency: 2.048 MHz
With a high level on this port the transmit lines XL1/2 or
XDOP/N are set directly into tristate. This pin function is
logically ored with register XPM2.XLT.
a
-bits within the data stream on XDI.
279
DS1.1, 2003-10-23
PEF 2256 H/E
E1 Registers
FALC
®
56