PEF2256 INFINEON [Infineon Technologies AG], PEF2256 Datasheet - Page 285

• Manufacturer Part Number: PEF2256
• Description: E1/T1/J1 Framer and Line Interface Component for Long- and Short-Haul Applications
• Manufacturer: INFINEON [Infineon Technologies AG]

XTF3
XME3
SRES3
Common Configuration Register 3 (Read/Write)
Value after reset: 00
CCR3
RADD2
RCRC2
User’s Manual
Hardware Description
7
RADD2 RCRC2 XCRC2
Transmit Transparent Frame - HDLC Channel 3
Initiates the transmission of a transparent frame without HDLC
framing.
Transmit Message End - HDLC Channel 3
Indicates that the data block written last to the XFIFO3 completes the
current frame. The FALC
properly by appending the CRC and the closing flag sequence to the
data.
Signaling Transmitter Reset - HDLC Channel 3
The transmitter of the signaling controller is reset. XFIFO3 is cleared
of any data and an abort sequence (seven 1s) followed by interframe
time fill is transmitted. In response to SRES3 an XPR3 interrupt is
generated.
This command can be used by the CPU to abort a frame currently in
transmission.
Receive Address Pushed to RFIFO2
If this bit is set, the received HDLC channel 2 address information (1
or 2 bytes, depending on the address mode selected via
MODE2.MDS02) is pushed to RFIFO2. This function is applicable in
non-auto mode and transparent mode 1.
Receive CRC ON/OFF - HDLC Channel 2
Only applicable in non-auto mode.
If this bit is set, the received CRC checksum is written to RFIFO2
(CRC-ITU-T: 2 bytes). The checksum, consisting of the 2 last bytes in
the received frame, is followed in the RFIFO2 by the status
information byte (contents of register RSIS2). The received CRC
checksum will additionally be checked for correctness. If non-auto
mode is selected, the limits for “Valid Frame” check are modified.
H
285
®
can terminate the transmission operation
ITF2
XMFA2
RFT12
DS1.1, 2003-10-23
PEF 2256 H/E
RFT02
E1 Registers
0
FALC
(8B)
®
56