PEF2256 INFINEON [Infineon Technologies AG], PEF2256 Datasheet - Page 357
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PEF2256
Manufacturer Part Number
PEF2256
Description
E1/T1/J1 Framer and Line Interface Component for Long- and Short-Haul Applications
Manufacturer
INFINEON [Infineon Technologies AG]
Datasheet
1.PEF2256.pdf
(518 pages)
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Receive Time Slot Register 1 to 4 (Read/Write)
Value after reset: 00
RTR1
RTR2
RTR3
RTR4
TS(31:0)
User’s Manual
Hardware Description
TS16
TS24
TS0
TS8
7
Time Slot Register
These bits define the received time slots on the system highway port
RDO to be extracted. Additionally these registers control the RSIGM
marker which can be forced high during the corresponding time slots
independently of bit CCR1.EITS.
A one in the RTR(4:1) bits samples the corresponding time slot in the
RFIFO of the signaling controller, if bit CCR1.EITS is set.
Assignments:
SIC2.SSC2 = 0: (32 time slots/frame)
TS0
SIC2.SSC2 = 1: (24 time slots/frame)
TS0
0 =
1 =
TS17
TS25
TS1
TS9
H
, 00
The corresponding time slot is not extracted and stored in the
RFIFO.
The contents of the selected time slot is stored in the RFIFO.
Although the idle time slots can be selected. This function is
only active, if bits CCR1.EITS is set.
The corresponding time slot is forced high on pin RSIGM.
H
time slot 0,TS31
time slot 0,TS23
, 00
TS10
TS18
TS26
TS2
H
, 00
H
TS11
TS19
TS27
TS3
357
time slot 31
time slot 23
TS12
TS20
TS28
TS4
TS13
TS21
TS29
TS5
TS14
TS22
TS30
TS6
DS1.1, 2003-10-23
T1/J1 Registers
PEF 2256 H/E
TS15
TS23
TS31
TS7
0
FALC
(0C)
(0D)
(0E)
(0F)
®
56
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